Gurmeet Singh
Sunnyvale, CA 94086
Professional Experience
[2022-2024] PPA Engineer, Intel Corp.
- Advanced node RTL->GDSII flow development, Implementation, PPA benchmarking and optimization of industry standard IPs; Development of infrastructure and execution of PPA and other metrics’ automated collection, analysis and visualization using R/GGPlot2 and Python/Pandas/Seaborn.
[2020-2022] Contractor, Samsung Austin R&D Center
- 4nm RTL-to-GDSII Physical Design to tapeout, 3nm Flow development
[2018-2019] Esperanto Technologies
- Machine Learning SoC: 7nm Physical Design and Methodology (timing corners, margins, clocking methodology, library cells and level shifters’ analysis, 1.1M gate PnR), Global Clock Distribution: clock tree design/modeling/spice-simulation and ICC2 implementation
[2015-2017] ZGlue Inc.
- Hierarchical implementation of a tile based design including floorplanning, power grid, place and route, lec and physical verification. Silicon success.
- Physical design methodology; Cadence Innovus based netlist-to-gds automated implementation flow, LEC methodology and LVS/DRC flow development.
- Mixed-signal CAD, Programming in SKILL language, Detailed Abstract generation for through-block routability.
- Setup Virtuoso QRC extraction flow, set up and run full chip STA with Tempus, set up and run LEC on chip. Silicon success.
[2015-present] Machine Learning
[2013-14] Qualcomm Technologies
- 40nm ASIC: Top level floorplan and power grid design with multiple power domains for a mixed signal design, automated floorplan generation with Tcl. Wrote power intent CPF from scratch. Full chip formal (LEC) and low power (CLP) verification using Cadence tools. Apache Redhawk EM/IR debug and fixes. Received Qualstar certificates. Beat the schedule.Silicon success (WCD9335).
[2008-13] Consultant/Engineer
- 14nm/FinFET: Developed complete,automated rtl2gds flow using Cadence tools. Using the same flow, implemented an ARM A9/Neon design @ 2.4GHz.
- 28nm DDR-PHY IP final implementation runs for tapeout.
- Developed a 40nm automated, optimized, tapeout ready, Cadence based netlist-to-gds implementation flow. Wrote Tcl scripts for a correct by construction, tunable flow used for all blocks.
- Developed automated, tapeout ready, STA setup using Primetime-SI using Tcl/Perl scripts.
- Implemented several large blocks at tapeout quality using the above flow ; the resulting GDSII were timing, LEC, LVS/DRC clean. Silicon success.
- Helped grow the size and capability of the physical design team and lead technical direction.
- Setup 40nm Cadence based, automated, tapeout ready, block level implementation flow.
- Hierarchical physical implementation flow in 65nm technology using Cadence.
- 65nm Telecom ASIC: Implementation of two large blocks using Magma. Silicon Success.
- 65nm WiFi ASIC: Implementation of large block using Magma. Silicon Success.
- 65nm WiFi ASIC: Full chip EM/IR signoff using Apache-Redhawk. Silicon Success.
[2006-08] Teranetics
- 130nm/65nm 10GBASE-T Phy ASIC: Implement many large blocks, some using x-route. Automate implementation using place and route tools, static timing analysis, logical equivalence and physical verification flows. Power estimation; power reduction using special cells. Silicon Success.
[2004-06] Airgo Networks
- Multiple WiFi ASICs: Implement many blocks using Magma. Automate PTSI STA, formal (LEC) and Calibre physical verificatino flows. Full chip EM/IR flow development and signoff using Apache-Redhawk. Tapeout signoff/jobview. Multiple ECOs, I/O Spice sims and silicon failure analysis, IP integration, Methodology, project management. Silicon success.
- 1.2/1.8GHz Efficeon CPUs: Implement Hyper-Transport PnR blocks; Register File custom circuit design. Peformed dozens of all layer and metal-only ECOs. Setup latch compatible STA flow. Array and noise methodologies. One patent awarded on a Repeater Circuit. Silicon Success (#1 and #2).
[1999-01] Sun Microsystems
- UltraSparc V CPU: CAM Register File (4 write, 2 read, 1 compare) design, modeling and verification
- 1.2GHz UltraSparc III CPU: Ported a dozen 130nm dynamic circuit blocks, including adders up to 64-bits, from 180nm to 130nm. Wrote a C language module to create a timing model through Pathmill API. Silicon success.
[1997-99] Intel Corporation
- 833MHz Pentium III Xeon CPU: High speed dynamic circuit design for L2$ ECC, L2$ STA/EM/IR verification. Silicon success.
- 600 MHz Pentium III CPU : GTL I/O circuit design. One patent disclosure. Silicon success.
[1994-97] STMicroelectronics
- Circuit Design of a high performance 32kx8, and a low power 128kx8 SRAM. Silicon success. CAD setup for custom circuit design. Reverse engineer a competitor register file and re-implement, verify functionality (including leap years, Y2K etc.) using verilog switch level simulation. Silicon success.
Education:
[2015-2018]: Coursera Courses
- Neural Networks and Deep Learning
- Machine Learning
- Machine Learning With Big Data
- Practical Machine Learning
- Structuring Machine Learning Projects
- Improving Deep Neural Networks: Hyperparameter tuning, Regularization and Optimization
- Convolutional Neural Networks
- Sequence Models
- How Google does Machine Learning
- Launching into Machine Learning
- Intro to TensorFlow
- R Programming
- Statistical Inference
- Reproducible Research
- Regression Models
- Functional Programming Principles in Scala
- Object Oriented Programming in Java
- Financial Markets
- Graph Analytics for Big Data
- Hadoop Platform and Application Framework
- The Data Scientist’s Toolbox
- Getting and Cleaning Data
- Exploratory Data Analysis
- Developing Data Products
- Introduction to Big Data
- Introduction to Big Data Analytics
- HTML, CSS and Javascript for Web Developers
